Large-scale electronic structure simulations coupled to an empirical modeling approach are critical as they present a robust way to predict various quantum phenomena in realistically sized nanoscale structures that are hard to be handled with density functional theory. For tight-binding (TB) simulations of electronic structures that normally involve multimillion atomic systems for a direct comparison to experimentally realizable nanoscale materials and devices, we show that graphical processing unit (GPU) devices help in saving computing costs in terms of time and energy consumption. With a short introduction of the major numerical method adopted for TB simulations of electronic structures, this work presents a detailed description for the strategies to drive performance enhancement with GPU devices against traditional clusters of multicore processors. While this work only uses TB electronic structure simulations for benchmark tests, it can be also utilized as a practical guideline to enhance performance of numerical operations that involve large-scale sparse matrice.
ABOUT THE SPEAKER: Hoon Ryu received B.S./M.S./Ph.D from School of Electrical Engineering, Seoul National Univerisity Dept. of Electrical Engineering, Stanford University / School of Electrical and Computer Engineering, Purdue University. He was with System LSI Division, Samsung Electronics, and currently is with Korea Institute of Science and Technology Information, where he is in charge of PI of Intel Parallel Computing Center. His specialty and main research interests are in simulation of advanced semiconductor devices with aids of numerical analysis coupled to high performance computing.
서울대학교 전기공학부에서 학사학위를 취득하고 Stanford 대학교와 Purdue 대학교에서 반도체 소자 전산모사를 전공으로 석.박사 학위를 취득했다. 삼성전자 DS부문 System LSI 사업부를 거쳐 현재 한국과학기술정보연구원 슈퍼컴퓨팅본부에 재직하고 있다. 한국 인텔 초병렬컴퓨팅 활용연구사업 책임자를 맡고 있으며, 주요 전문분야는 수치해석을 이용한 차세대 반도체 소자 특성 모사이다.
