NVIDIA 6G Developer Day

Learn how to build, simulate, and deploy AI‑native RAN solutions for 6G.

Introduction
Agenda
Speakers
Resources

Introduction
Agenda
Speakers
Resources

NVIDIA’s 6G Developer Day 2025 brings together developers and researchers to explore the latest 6G tools. Across six sessions, learn how to progress from early prototypes to full deployment of AI‑native RAN solutions.

Join us virtually on December 10 for expert‑led talks, Q&A, and practical guidance to take the next step in your 6G journey.

Event Information

Date: Wednesday, December 10
Time: 8 a.m. – 1 p.m. PT
Location: Virtual

Event Information

On-Demand Webinar
Duration: 5 hours

Agenda

8 a.m. PT

Introduction to NVIDIA 6G Research Portfolio

Introducing NVIDIA’s latest 6G research tools and the resources and capabilities available for developers.

CC Chong, Senior Director and Head of Aerial Product Management, NVIDIA

8:15 a.m. PT

From Theory to Practice—Prototyping 6G With the NVIDIA Sionna Research Kit

Learn how to prototype AI-native RAN algorithms under real-time 5G constraints using a GPU-accelerated research platform with over-the-air testing capabilities.

Sebastian Cammerer, Senior Research Scientist, NVIDIA

9 a.m. PT

Designing a Modular 6G System Using NVIDIA Aerial™ Framework

Get started with the new, modular Aerial Framework for writing 6G signal blocks and pipelines.

Michael Roe, Principal Engineer, NVIDIA

10 a.m. PT

Generating Performant 6G GPU-Accelerated Code From High-Level Programming Languages

Go from Python-based 6G signal blocks and pipelines to performant, real-time, GPU-accelerated code with a new toolchain.

Roy Timo, Principal Engineer, NVIDIA

11 a.m. PT

Optimizing 6G Performance With CUDA and NVIDIA DOCA

Explore how to build efficient, 6G workloads by optimizing design patterns to achieve low-latency, high-throughput processing with CUDA and NVIDIA DOCA™.

Harsha Banuli, Principal Software Engineer, NVIDIA

12 p.m. PT

Simulating 6G With NVIDIA Aerial Omniverse™ Digital Twin

Understand how to simulate 6G CUDA code using a RAN digital twin for scalable 6G network testing and development.

Tommaso Balercia, Principal Engineer, NVIDIA

Speakers

CC Chong
Senior Director and Head of Aerial Product Management
NVIDIA

CC Chong is the senior director and head of Aerial product management at NVIDIA. Before joining NVIDIA, she was senior director and GM of the wireless and access business unit in the Intel Programmable Solutions Group. In that role, she participated in key pioneering programs, bringing virtualization to telecom infrastructure. CC has spent much of her career focusing on innovation within the communications space with Intel, Samsung, SK Telecom, Huawei Mobile, Orange, and NTT DOCOMO. She received her Ph.D. in electronics & electrical engineering from The University of Edinburgh, UK and her B.Eng First Class in electronics & electrical engineering from the University of Manchester. She has 40 granted and pending U.S. patents. CC has co-authored two book chapters and published more than 100 international journals, conference papers, and international standard contributions. Additionally, she was awarded the Ten Outstanding Young Malaysian Awards under the category “Scientific and Technological Development” in 2006.

Sebastian Cammerer
Senior Research Scientist
NVIDIA

Sebastian Cammerer is a senior research scientist at NVIDIA, working on the intersection of wireless communications and machine learning. Before joining NVIDIA, he received his Ph.D. in electrical engineering and information technology from the University of Stuttgart, Germany, in 2021. Sebastian is one of the maintainers and core developers of the Sionna open-source link-level simulator. His main research topics are machine learning for wireless communications and channel coding. Further research interests include parallel computing for wireless signal processing and information theory. He has received the VDE ITG Dissertations award 2022, the IEEE SPS Young Author Best Paper Award 2019, the Best Paper Award of the University of Stuttgart 2018, the Anton- und Klara Röser Preis 2016, the Rohde & Schwarz Best Bachelor Award 2015, and third prize in the Nokia Bell Labs Prize 2019.

Michael Roe
Principal Engineer
NVIDIA

Michael Roe is a principal engineer at NVIDIA, where he focuses on developing GPU-accelerated software for wireless systems. He holds bachelor’s degrees in physics and electrical and computer engineering from Ohio State University and a Ph.D. in electrical engineering from the University of California, Berkeley. His areas of interest include real-time software, radio frequency (RF) and antenna systems, and radio access network (RAN) design.

Roy Timo
Principal Engineer
NVIDIA

Roy Timo is a principal engineer at NVIDIA, where he helps advance the AI Aerial platform. Previously, he headed Ericsson’s AI and Digital Twins group: He drove ASIC-based AI model design and 5G digital twin development, and he led Ericsson’s AI team for 3GPP Release 18. Roy was an Alexander von Humboldt Postdoctoral Fellow at the University of Munich and has a Ph.D. in information theory from the Australian National University.

Harsha Banuli
Principal Software Engineer
NVIDIA

Harsha Banuli is a principal software engineer at NVIDIA and currently leads the RAN Performance Engineering team, driving system-level innovations for predictable, low-latency workload execution on NVIDIA platforms. His expertise lies in designing scalable, high-performance systems, including software-hardware co-design. He is passionate about advancing technologies that combine performance and efficiency to create real-world impact. He earned his master’s degree from the University of Southern California, Los Angeles.

Tommaso Balercia
Principal Engineer
NVIDIA

Tommaso Balercia is a principal engineer and the lead architect of the RAN digital twin at NVIDIA. He holds an M.Sc (Hons.) in electrical engineering from Universita’ Politecnica delle Marche (Italy) and a Ph.D from Technische Universität Braunschweig (Germany). His areas of interest cover computational electromagnetics, digital signal processing, and simulation technology.